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4 commits

Author SHA1 Message Date
Shay
b40422e9db perf(rust): versor_apply f64 parity port — 29x over Python, bit-identical
Closes the last open Rust parity gate from ADR-0020.

Kernel: new versor_apply_closed_f64 in core-rs/src/versor.rs performs
the full sandwich V·F·rev(V) + closure in f64, mirroring Python's
algebra.versor.versor_apply + _close_applied_versor exactly:
  - no null-vector early branch (Python doesn't have one)
  - unitize_versor with dense-support seed fallback gate
  - post-unitize versor_condition < 1e-6 recheck
  - seed_to_rotor on failure, passthrough as last resort

PyO3 binding: versor_apply_with_closure_f64 accepts/returns float64
arrays through new extract_f64_slice / f64_array_to_numpy helpers.
algebra/backend.py::versor_apply routes through it under CORE_BACKEND=rust.

Parity gate re-enabled (was skipped pending this port). 8/8 bit-
identical across normalized hot-path + identity-versor cases.

Bench (5000 iters, runtime hot path):
  python: 213.0 us/call
  rust:     7.4 us/call  → 28.8x speedup

All lanes green: algebra 132 (was 124+8skip), smoke 54, runtime 19,
cognition 57, teaching 17, packs 6. Cognition eval 100% across all metrics.

PROGRESS.md updated: versor_apply marked passing; Phase 5 Rust parity
track now 5/5 surfaces gated and enabled.
2026-05-16 20:43:01 -07:00
Shay
70e58ce446 feat(adr-0020): parity gates for cga_inner, geometric_product, versor_condition, versor_apply
ADR-0020 next-level: close the parity-gate hole on the four remaining
ungated Rust surfaces.

Gates landed (subprocess-based, raw f32/f64 byte equality):
  cga_inner         — 14/14 bit-identical (random + basis blades + self-norm)
  geometric_product — 15/15 bit-identical (random + basis blades + scalar identity)
  versor_condition  —  9/9  bit-identical AFTER kernel fix
  versor_apply      —  8/8  intentionally skipped (see below)

Kernel fix: versor_condition_raw

  The Python source-of-truth (algebra.versor.versor_unit_residual) folds
  the geometric product + identity subtraction + Frobenius norm in f64.
  The Rust kernel was folding in f32, drifting by 1 ULP on out-of-shell
  inputs. Rewrote versor_condition_raw to promote inputs to f64, use the
  existing geometric_product_f64/reverse_f64 building blocks, and cast
  only the final scalar back to f32. Python is canonical per CLAUDE.md
  sequencing rule 5.

Honest disable: versor_apply

  The Rust versor_apply_closed diverges structurally:
    (1) precision    — f32 sandwich vs Python's f64 throughout
    (2) closure form — Rust has a null-vector early branch + no
                       post-unitize condition recheck; Python is the
                       inverse (no null branch; recheck + seed-rotor
                       fallback)
  Per ADR-0020 "default-off until parity passes", the Rust dispatch for
  versor_apply is disabled in algebra/backend.py with a pointer to the
  gate. The parity tests are skipped with explicit reason. The follow-up
  f64 port is documented in the ADR's new Parity status table.

Lane registration: all four parity files added to --suite algebra.
After: algebra 124 passed, 8 skipped (was 86). All other lanes green:
smoke 54, runtime 19, cognition 57, teaching 17, packs 6. Cognition
eval 100%.
2026-05-16 20:37:58 -07:00
Shay
2da4a5b316 docs: accept ADR-0020 (Option C) — Phase 5 opens, Rust parity track armed
ADR-0020 moves to Accepted. Phase 5 — Curriculum Era opens
2026-05-16 on the Python runtime. Rust backend parity port
runs as a parallel track, per-surface bit-identity gated,
default-off until each surface's parity test passes on main.

First Phase 5 lane: 5.1 English fluency v5 OOD.
First Rust parity port: vault_recall.
2026-05-16 16:49:45 -07:00
Shay
4d778c01fc docs(phase4): exit memo + ADR-0020 Phase 5 / Rust parity sequencing (proposed)
Phase 4 exited 2026-05-16. All three planned lanes shipped:
sample_efficiency (one-shot-per-correction, replay 1.0),
long_context_cost (slope 0.99 linear after ADR-0019 Stage 1),
multi_agent_composition (15/15 public, composition does not
launder identity violations).

PROGRESS.md updated with full Phase 4 narrative and exit
checklist.

ADR-0020 opens the next sequencing decision: Phase 5
(curriculum era) vs. Rust backend parity port. Three options
laid out (A: Phase 5 first, B: Rust first, C: parallel with
per-surface bit-identity gating). Recommendation: Option C.
Status remains Proposed pending user confirmation.
2026-05-16 16:48:46 -07:00