Shay
|
4183a675a5
|
docs(adr): Apple Silicon UMA acceleration lane roadmap (ADR-0235) (#905)
Define staged PR stack from #904 benchmark foundation through Rust
baseline, scalar zero-copy cleanup, optional MLX/Metal experiments,
Workbench evidence surfacing, and multimodal/AMR structured-evidence
design — with parity gates, non-claims, and merge ordering.
Documentation only; no runtime backend changes.
|
2026-06-24 12:47:14 -07:00 |
|