Default branch

4308519ca9 · feat(ask): add served ASK artifact adapter · Updated 2026-06-09 19:49:52 +00:00

Branches

main
Some checks failed
lane-shas / verify pinned lane SHAs (push) Failing after 31s
full-pytest / full pytest (-m "not quarantine" -n 2) (push) Failing after 15m53s

d4eca6c401 · docs: add fallback to tea CLI if Forgejo MCP is unavailable · Updated 2026-07-06 15:55:23 +00:00    core-labs

0
492
fix/cga-substrate-final-cleanups
Some checks failed
lane-shas / verify pinned lane SHAs (pull_request) Failing after 13m0s
workbench-ui / build + vitest (pull_request) Failing after 2m3s
workbench-ui / playwright smoke (pull_request) Failing after 40s
smoke / smoke (-m "not quarantine") (pull_request) Failing after 17m39s

9c8807e575 · chore: ignore local .mcp.json configuration file · Updated 2026-07-05 21:46:37 +00:00    core-labs

0
493
#1 Open

54e2d77416 · fix(tests): restore test pipeline stability for CGA substrate · Updated 2026-07-05 14:24:20 +00:00    core-labs

0
489

8d1eb8af5d · Lane 5: UI Trace Updates for Geometric Invariants · Updated 2026-07-04 22:12:48 +00:00    core-labs

0
480

f6c1f01a13 · Lane 4: Registry Consolidation (language_packs to packs) · Updated 2026-07-04 22:11:28 +00:00    core-labs

0
480

a5f67f95a4 · feat(demos): Implement ADR-0218 PR D proof-carrying promotion demo (#927) · Updated 2026-07-03 20:01:49 +00:00    core-labs

0
476

3b37d439e2 · chore: cleanup CLI extraction and unreachable code · Updated 2026-07-03 19:31:56 +00:00    core-labs

0
483

03c87e680b · fix(core): lock python and extend rust cga surface · Updated 2026-07-02 22:20:14 +00:00    core-labs

0
473

c80b9cbc95 · fix: green test-fast suite, consolidate ADR graph under docs/adr, and complete governance cohesion anchors · Updated 2026-07-01 00:55:36 +00:00    core-labs

0
472

d6dbd2403e · docs: beef up docs/README.md navigation · Updated 2026-06-30 23:54:34 +00:00    core-labs

0
473

284e4c5717 · test(workbench-ui): fix UI and keyboard tests for Apple UMA route integration · Updated 2026-06-24 22:25:07 +00:00    core-labs

0
462

cb41aedd66 · feat(workbench): expose Apple UMA report route · Updated 2026-06-24 21:38:37 +00:00    core-labs

0
459

ab9d6f2e57 · feat(bench): wire MLX exact recall into Apple UMA report · Updated 2026-06-24 20:57:46 +00:00    core-labs

0
456

ba7cb7c98c · docs(bench): add MLX local validation handoff · Updated 2026-06-24 20:44:20 +00:00    core-labs

0
459

21d90b2674 · Patch PR #907 to make scalar Rust inputs fully zero-copy without stack array copies · Updated 2026-06-24 20:25:21 +00:00    core-labs

0
454

59b2a8f526 · Patch PR #907 to make scalar Rust inputs fully zero-copy without stack array copies · Updated 2026-06-24 20:14:49 +00:00    core-labs

0
454

da92c1c3c0 · feat(rust): scalar Cl(4,1) zero-copy input boundary (ADR-0235 PR C) · Updated 2026-06-24 20:02:06 +00:00    core-labs

0
453

da92c1c3c0 · feat(rust): scalar Cl(4,1) zero-copy input boundary (ADR-0235 PR C) · Updated 2026-06-24 20:02:06 +00:00    core-labs

0
453

81bffcad02 · feat(bench): Rust-enabled Apple UMA baseline report lane (PR B) · Updated 2026-06-24 19:43:49 +00:00    core-labs

0
451

b198807f06 · docs(adr): Apple Silicon UMA acceleration lane roadmap (ADR-0235) · Updated 2026-06-24 19:38:04 +00:00    core-labs

0
451